Computer Organization & Architecture 2025

(a) The unit responsible for fetching, decoding, and executing instructions is

1. ALU
2. Control Unit
3. Memory Unit
4. I/O Unit

(b) Which addressing mode uses the contents of a register to determine the effective address?

1. Signed integers
2. Indirect addressing
3. Direct addressing
4. Register addressing

(c) Two's complement representation is primarily used for

1. Signed integers
2. ASCII characters
3. Instruction opcodes
4. Floating point numbers

(d) Booth's algorithm is used for

1. Floating point operations
2. Division
3. Character coding
4. Multiplication

(e) In floating point representation, the part representing significant digits is called

1. Mantissa
2. Exponent
3. Sign bit
4. Bias

(f) x86 architecture belongs to which processor family?

1. RISC
2. EPIC
3. CISC
4. ARM

(g) Memory chips used in main memory are typically

1. Optical memory
2. Magnetic tapes
3. Flash
4. DRAM

(h) USB is an example of

1. Networking device
2. Standard I/O interface
3. Storage device only
4. Wireless protocol

(i) Pipeline speedup ideally increases with

1. Number of control units
2. Number of pipeline stages
3. Size of RAM
4. Size of cache

(j) In cache memory, FIFO and LRU are examples of

1. Mapping techniques
2. Replacement algorithms
3. Addressing techniques
4. Write policies

(a) Explain the functional blocks of a computer with neat diagrams: CPU, Memory, and I/O subsystems.

(b) Explain addressing modes with examples. Compare at least five different addressing techniques.

(a) Explain all types of number representations: signed integers, fixed point, floating point, and character codes.

(b) Describe floating point arithmetic and explain overflow, underflow, normalization, and rounding.

(a) Describe shift-and-add multiplication and Booth's multiplication algorithm with examples.

(b) Explain the architecture of x86 processors. Discuss its registers, addressing modes, and instruction format.

(a) Describe the design of a simple hypothetical CPU including instruction set, datapath, and control design.

(b) Explain semiconductor memory organization with diagrams.

(a) Explain I/O transfer techniques: program-controlled I/O, interrupt-driven I/O, and DMA.

(b) Describe different types of interrupts: hardware, software, vectored, non-vectored, and exceptions.

(a) Explain the basic concepts of pipelining, including speedup and throughput. Discuss pipeline hazards.

(b) Describe parallel processors and the problem of cache coherency in shared memory systems.

(a) Explain cache memory organization. Discuss mapping techniques (direct, associative, set-associative), replacement algorithms, and write policies.

(b) Explain signed number representation using sign-magnitude, 1's complement, and 2's complement. Include advantages and disadvantages of each.

(a) Explain the organization of semiconductor memories such as SRAM and DRAM. Discuss refresh cycles, access times, and their applications.

(b) Discuss memory hierarchy design principles. Explain how access time, cost, and size influence memory organization.