Digital Electronics 2025

(a) A Programmable Logic Array consists of

1. Fixed AND and fixed OR arrays
2. Programmable AND and programmable OR arrays
3. Fixed AND and programmable OR arrays
4. Programmable AND and fixed OR arrays

(b) The invalid condition in an SR flip-flop occurs when

1. $S = 0, R = 0$
2. $S = 0, R = 1$
3. $S = 1, R = 0$
4. $S = 1, R = 1$

(c) A ripple counter is also known as

1. Synchronous counter
2. Up-down counter
3. Asynchronous counter
4. Ring counter

(d) The resolution of an n-bit DAC is

1. $2^n$
2. $1/(2^n - 1)$
3. $1/2^n$
4. $2^{n-1}$

(e) Which memory is volatile in nature?

1. ROM
2. RAM
3. PROM
4. EPROM

(f) Find the 2's complement of the binary number 1010

1. 0101
2. 0110
3. 1110
4. 0111

(g) Which logic family is most suitable for battery-operated portable devices, and why?

1. TTL – high speed
2. RTL – low complexity
3. CMOS – low power consumption
4. DTL – low cost

(h) A Multiplexer (MUX) is a device that

1. Converts parallel data into serial
2. Performs arithmetic operations
3. Selects one input from many and routes it to the output
4. Stores data

(i) Evaluate the Boolean expression $Y = A + A \cdot B$

1. $A$
2. $A + B$
3. $B$
4. $0$

(j) What is the output of a half adder for inputs $A = 1$ and $B = 1$?

1. $\text{Sum} = 0, \text{Carry} = 1$
2. $\text{Sum} = 1, \text{Carry} = 0$
3. $\text{Sum} = 1, \text{Carry} = 1$
4. $\text{Sum} = 0, \text{Carry} = 0$

(a) Implement the logic expression using a suitable Multiplexer $F(A,B,C,D) = \Sigma(0,1,3,4,8,9,15)$. Using variables A, C, and D as select lines.

(b) Describe the architecture and working of Programmable Logic Array.

(a) Design a synchronous counter using a T-flip-flop that counts $0 \rightarrow 3 \rightarrow 1 \rightarrow 2 \rightarrow 0$

(b) Describe the dual slope ADC and explain why it is suitable for digital voltmeters.

(a) Simplify the Boolean function: $F(A,B,C,D) = \Sigma(0,2,4,5,6)$.

(b) Describe the CMOS logic family and its advantages over TTL. Discuss its role in modern VLSI design.

(a) Implement a full-adder circuit with a decoder and two OR gates.

(b) Compare PLA, PAL, and ROM-based implementations.

(a) Design the logic expression $F = A(B + CD) + BC'$ using NAND gates only.

(b) Describe charge-coupled device memory and its working principle.

(a) Explain the working of encoders and decoders. Design a 3-to-8 decoder logic circuit.

(b) Explain the concept of memory organization and operation in digital systems.

(a) Explain the concept of the race-around condition in the JK flip-flop and suggest methods to eliminate it.

(b) Explain the R-2R ladder DAC and compare it with the weighted resistor DAC.

Write short notes on any two of the following:

(a) Flip flops

(b) sample-and-hold circuit

(c) PROM, EPROM and EEPROM

(d) BCD to Gray code conversion