Introduction to VLSI Design 2025

(a) MOSFET capacitances depend on:

1. Channel doping only
2. Biasing conditions
3. Layout rules
4. Mobility of carriers

(b) Bipolar transistors offer:

1. High input impedance
2. Low noise margin
3. High speed and drive strength
4. High leakage

(c) BiCMOS consumes more power than CMOS because:

1. Bipolar devices have static bias currents
2. High interconnect parasitics
3. CMOS scaling issues
4. Low threshold voltages

(d) SRAM cell is typically built using:

1. 2 transistors
2. 6 transistors
3. 4 transistors
4. 8 transistors

(e) Arithmetic circuits include:

1. Shifters
2. Registers
3. Adders & multipliers
4. Both (i) & (iii)

(f) PTL stands for:

1. Pseudo Transistor Logic
2. Power Tuned Logic
3. Pass Transistor Logic
4. Pre-charge Ternary Logic

(g) TSPC registers are used for:

1. Multi-phase clocking
2. Leakage reduction
3. Single-phase high-speed clocking
4. Memory design

(h) In Complementary CMOS logic, power is mainly consumed during:

1. Static state
2. Body biasing
3. Switching activity
4. Leakage only

(i) Low-power design techniques target reduction of:

1. Channel length
2. Parasitic capacitances only
3. Switching activity and supply voltage
4. Gate count

(j) Supply voltage scaling mainly affects:

1. VTC shape
2. Layout parasitics
3. Speed and noise margin
4. Channel doping

Explain the MOSFET threshold voltage and derive expressions for the factors affecting it including body bias effect.

(a) Derive the static characteristics and noise margins of a CMOS inverter.

(b) Explain latch-up in CMOS, methods of prevention and layout considerations.

(a) Discuss propagation delay estimation using the Elmore delay model.

(b) Describe low-power design techniques in CMOS circuits.

(a) Explain pseudo-NMOS logic and compare it with CMOS logic.

(b) Discuss Domino logic operation and its derivatives.

(a) Describe the design and working of a CMOS shifter.

(b) Compare SRAM and DRAM in terms of speed, area, leakage and applications.

(a) Explain the design challenges and applications of BiCMOS logic circuits.

(b) Discuss static and dynamic behaviour of BiCMOS circuits.

(a) Explain CMOS layout elements, design rules and parasitics due to wires and vias.

(b) Discuss channel-length modulation and short channel effects in deep sub-micron MOSFETs.

Explain the effect of process variation and supply scaling on inverter performance.