Giving circuits a memory - flip-flops, registers and the clock
Combinational circuits forget everything instantly. Here's how a tiny feedback loop lets a circuit remember one bit, and how a clock signal keeps millions of them in sync.
The problem with forgetting everything
Every circuit from the last lesson computes its output purely from its current inputs. The instant an input changes, the output changes too, with zero memory of what came before. But a computer clearly needs to remember things: the contents of a variable, the next instruction to run, the running total of a sum. We need a circuit that can hold a value even after its inputs go away.
The trick: feed the output back into the input
The core idea behind memory in digital circuits is surprisingly simple: take a gate's output and wire it back around into its own input. This creates a loop that can "latch" onto a value and hold it indefinitely, as long as power stays on.
The simplest version is called an SR latch (Set-Reset latch), built from two NOR (or NAND) gates cross-wired so each one's output feeds the other one's input. It has two inputs, S (set) and R (reset):
- Pulse S to 1 momentarily → the latch stores a 1, and keeps storing it even after S goes back to 0.
- Pulse R to 1 momentarily → the latch stores a 0, and keeps storing it even after R goes back to 0.
- Leave both at 0 → the latch just holds whatever it last stored, indefinitely.
This is genuinely the entire idea of digital memory: a loop that holds its state until deliberately told to change.
From latch to flip-flop: adding a clock
An SR latch has a problem: it reacts to its inputs immediately and continuously, which makes it hard to coordinate thousands of them changing at exactly the same moment. The fix is the flip-flop — a latch that only updates on a clock edge (the precise instant a clock signal switches from 0 to 1, called the rising edge).
Think of a clock signal as a metronome ticking at a fixed rate, say a billion times a second (1 GHz). A flip-flop is like a very disciplined student who only writes down a new answer the exact instant the metronome ticks, and ignores any changes to the question in between ticks. This synchronization is what allows millions of flip-flops across an entire CPU to update in lockstep, so the whole chip advances through its work in clean, predictable, discrete steps rather than a chaotic continuous blur.
The most common type used inside CPUs is the D flip-flop (Data flip-flop): whatever value is on its single data input at the moment of the clock edge gets copied to its output , and held there until the next edge.
From flip-flop to register
A single D flip-flop stores 1 bit. Line up 32 of them, all sharing the same clock signal, and you get a register: a small, extremely fast storage location that holds an entire 32-bit number, updating all 32 bits simultaneously on every clock tick.
D31 -> [DFF] -> Q31 (bit 31 of the register)
D30 -> [DFF] -> Q30 (bit 30 of the register)
... ...
D0 -> [DFF] -> Q0 (bit 0 of the register)
All 32 flip-flops share the same clock line, so they all update together.
Registers are the fastest storage a CPU has — faster even than the cache memory we'll study later — precisely because they're built from this simple flip-flop circuit sitting directly next to the ALU, with no addressing or searching required to read or write them. A typical CPU has a small number of registers, often 16 to 32, used to hold the values actively being worked on right now.
Why the clock speed matters (a first taste of the math)
The clock frequency, measured in Hertz (cycles per second), determines how often every flip-flop in the chip is allowed to update. A "3 GHz processor" ticks 3 billion times per second. The time between two ticks is the clock period:
At , the clock period is:
Every register in the chip gets, at most, this tiny sliver of time to receive a new stable value before the next tick demands the next update. This single number — how fast you can safely tick the clock — turns out to be tightly limited by how slow your slowest combinational circuit is (like that ripple-carry adder from the last lesson), which becomes hugely important once we discuss pipelining.
Common mistakes
- Confusing a latch and a flip-flop. A latch is level-sensitive (reacts continuously while enabled); a flip-flop is edge-sensitive (reacts only at the instant of a clock tick). CPUs are built almost entirely from flip-flops for predictability.
- Thinking "more registers" and "more memory" are the same problem. Registers are extremely fast but extremely few (dozens); the memory hierarchy lesson later covers the much larger, much slower storage tiers.
- Assuming clock speed alone measures performance. A 3 GHz chip that must wait on a slow circuit before each tick isn't actually 50% faster than a 2 GHz chip doing more useful work per tick — this becomes very concrete in the pipelining module.
Summary
Sequential circuits gain memory by feeding a gate's output back into its own input, forming a latch that holds a value indefinitely. Real CPUs use clocked D flip-flops instead of raw latches, so that every piece of memory across the chip updates in lockstep on a shared clock's rising edge. Lining up flip-flops side by side builds a register, the fastest storage a CPU has. The clock period sets the tiny time budget every circuit between two registers must finish its work within — a constraint that shapes almost every design decision in the rest of this course.